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PERFORMANCE FEATURES 6.25 ns Instruction Cycle Time, for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Computation and Memory Instructions Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle
DSP Microcomputer ADSP-2191M
Multifunction Instructions Pipelined Architecture Supports Efficient Code Execution Architectural Enhancements for Compiled C and C++ Code Efficiency Architectural Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, and Peripherals Flexible Power Management with User-Selectable Power-Down and Idle Modes
FUNCTIONAL BLOCK DIAGRAM
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS ADSP-219x DSP CORE CACHE 64 24-BIT
BLOCK0 BLOCK1 BLOCK2 BLOCK3
24 BIT ADDRESS DATA 24 BIT ADDRESS DATA 16 BIT DATA ADDRESS 16 BIT DATA ADDRESS
JTAG TEST & EMULATION
6
4
DAG1 4 16
4
DAG2 4 16
PROGRAM SEQUENCER EXTERNAL PORT PM ADDRESS BUS 24 I/O ADDRESS 18 ADDR BUS MUX 24 DMA CONNECT PM DATA BUS 24 16 16 I/O DATA I/O PROCESSOR DATA BUS MUX 16 DMA ADDRESS 24 DMA DATA 22
DM ADDRESS BUS
24
PX DM DATA BUS
DATA REGISTER FILE INPUT REGISTERS RESULT REGISTERS MULT 16 16-BIT BARREL SHIFTER ALU I/O REGISTERS (MEMORY-MAPPED) CONTROL STATUS BUFFERS DMA CONTROLLER
24 HOST PORT 18 SERIAL PORTS (3) 6 SPI PORTS (2) 2 UART PORT (1) 3 SYSTEM INTERRUPT CONTROLLER PROGRAMMABLE FLAGS (16) TIMERS (3)
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ADSP-2191M
INTEGRATION FEATURES 160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAM Dual-Purpose 24-Bit Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators Unified Memory Space Allows Flexible Address Generation, Using Two Independent DAG Units Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Enhanced Interrupt Controller Enables Programming of Interrupt Priorities and Nesting Modes SYSTEM INTERFACE FEATURES Host Port with DMA Capability for Glueless 8- or 16-Bit Host Interface 16-Bit External Memory Interface for up to 16M Words of Addressable Memory Space Three Full-Duplex Multichannel Serial Ports, with Support for H.100 and up to 128 TDM Channels with A-Law and -Law Companding Optimized for Telecommunications Systems Two SPI-Compatible Ports with DMA Support UART Port with DMA Support 16 General-Purpose I/O Pins with Integrated Interrupt Support Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulsewidth Measurement, and External Event Counter Capabilities Up to 11 DMA Channels Can Be Active at Any Given Time for High I/O Throughput On-Chip Boot ROM for Automatic Booting from External 8- or 16-Bit Host Device, SPI ROM, or UART with Autobaud Detection Programmable PLL Supports 1 to 32 Input Frequency Multiplication and Can Be Altered during Runtime IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 2.5 V Internal Operation and 3.3 V I/O 144-Lead LQFP and 144-Ball Mini-BGA Packages TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3 DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3 DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .9 Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9 UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . .10 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12 Instruction Set Description . . . . . . . . . . . . . . . . . . . .13 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13 Additional Information . . . . . . . . . . . . . . . . . . . . . . .15 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . 19 ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .41 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Environmental Conditions . . . . . . . . . . . . . . . . . . . .42 144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .44 144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .46 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .48 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .49
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ADSP-2191M
GENERAL DESCRIPTION
The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces. The ADSP-2191M architecture is code-compatible with DSPs of the ADSP-218x family. Although the architectures are compatible, the ADSP-2191M architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2191M more flexible and even easier to program. Indirect addressing options provide addressing flexibility-- premodify with no update, pre- and post-modify by an immediate 8-bit, two's-complement value and base address registers for easier implementation of circular buffering. The ADSP-2191M integrates 64K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to reduce power consumption. The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2191M operates with a 6.25 ns instruction cycle time (160 MIPS). All instructions, except single-word instructions, execute in one processor. The ADSP-2191M's flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2191M can: * Generate an address for the next instruction fetch * Fetch the next instruction * Perform one or two data moves * Update one or two data address pointers * Perform a computational operation These operations take place while the processor continues to: * Receive and transmit data through two serial ports * Receive and/or transmit data from a Host * Receive or transmit data through the UART * Receive or transmit data over two SPI ports * Access external memory through the external memory interface * Decrement the timers
DSP Core Architecture
uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The functional block diagram on page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. Register-usage rules influence placement of input and results within the computational units. For most operations, the computational units' data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference. A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2191M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within 64K word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch. Efficient data transfer in the core is achieved with the use of internal buses: * Program Memory Address (PMA) Bus * Program Memory Data (PMD) Bus * Data Memory Address (DMA) Bus * Data Memory Data (DMD) Bus * DMA Address Bus * DMA Data Bus
The ADSP-2191M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2191M assembly language REV. 0 -3-
ADSP-2191M
The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Boot memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2191M to fetch two operands in a single cycle, one from program memory and one from data memory. The DSP's dual memory buses also let the ADSP-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle.
DSP Peripherals Architecture
ADSP-2191M
CLO CK OR CRYSTAL T IMER OUT OR CAPTURE CLO CK MULTIPL Y AN D RAN GE BO OT AND OP MODE CL KIN XTA L CL KOUT ADD R21-0 DAT A15-8 T MR2-0 DAT A7-0 MS3-0 MSEL6-0/PF6-0 DF /PF7 BYPASS BMODE1-0 OPMO DE RD WR AC K
ADDRESS CONTROL DATA
EXT ERN AL MEMORY
( O PT I O N A L )
A DDR21-0 D ATA15-8 D ATA7-0 CS OE WE ACK BO OT MEMORY
( O PT I O N A L )
The functional block diagram on page 1 shows the DSP's on-chip peripherals, which include the external memory interface, Host port, serial ports, SPI-compatible ports, UART port, JTAG test and emulation port, timers, flags, and interrupt controller. These on-chip peripherals can connect to off-chip devices as shown in Figure 1. The ADSP-2191M has a 16-bit Host port with DMA capability that lets external Hosts access on-chip memory. This 24-pin parallel port consists of a 16-pin multiplexed data/address bus and provides a low-service overhead data move capability. Configurable for 8 or 16 bits, this port provides a glueless interface to a wide variety of 8- and 16-bit microcontrollers. Two chip-selects provide Hosts access to the DSP's entire memory map. The DSP is bootable through this port. The ADSP-2191M also has an external memory interface that is shared by the DSP's core, the DMA controller, and DMA capable peripherals, which include the UART, SPORT0, SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external port consists of a 16-bit data bus, a 22-bit address bus, and control signals. The data bus is configurable to provide an 8 or 16 bit interface to external memory. Support for word packing lets the DSP access 16- or 24-bit words from external memory regardless of the external data bus width. When configured for an 8-bit interface, the unused eight lines provide eight programmable, bidirectional general-purpose Programmable Flag lines, six of which can be mapped to software condition signals. The memory DMA controller lets the ADSP-2191M move data and instructions from between memory spaces: internal-to-external, internal-to-internal, and external-to- external. On-chip peripherals can also use this controller for DMA transfers. The ADSP-2191M can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power-down), two external (emulator and reset), and twelve user-defined (peripherals) interrupts. The programmer assigns a peripheral to one of the 12 user-defined interrupts. The priority of each peripheral for interrupt service is determined by these assignments. There are three serial ports on the ADSP-2191M that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of opera-
SPORT0 T CLK0 T FS0 SERIAL DEVICE
( O P T I O N A L)
A DDR21-0 D ATA15-8 D ATA7-0 BMS CS OE WE ACK BR BG BGH EXT ER NAL I/O MEMOR Y
( O P TI O N A L )
DT 0 RC LK0 RF S0 DR 0 SPORT1 T CLK1 T FS1
SERIAL DEVICE
( O P TI O N A L )
DT 1 RC LK1 RF S1 DR 1 SPORT2 T CLK2/SCK0 T FS2/MOSI0 SPI0 IOMS
A DDR17-0 D ATA15-8 D ATA7-0 CS OE WE ACK HOST PROCESSO R SPI1 H AD15-0 HA16
( O P TI O N A L )
SERIAL DEVICE
( O P T I O N A L)
DT 2/MISO0 RC LK2/SCK1 RF S2/ MO SI1 DR 2/MISO1
A DDR15-0/ D ATA15-0 ADDR16 CS0 CS1 RD WR ACK ALE
UART U ART DEVICE
( O P T I O N A L)
HCMS HCIOMS HRD HWR
RXD T XD
RESET 6 JT AG
HA CK H ALE HACK_P
Figure 1. System Diagram
tion. Each serial port can transmit or receive an internal or external, programmable serial clock and frame syncs. Each serial port supports 128-channel Time Division Multiplexing. The ADSP-2191M provides up to sixteen general-purpose I/O pins, which are programmable as either inputs or outputs. Eight of these pins are dedicated-general purpose Programmable Flag pins. The other eight of them are multifunctional pins, acting as general-purpose I/O pins when the DSP connects to an 8-bit external data bus and acting as the upper eight data pins when the DSP connects to a 16-bit external data bus. These Programmable Flag pins can implement edge- or level-sensitive interrupts, some of which can be used to base the execution of conditional instructions.
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Three programmable interval timers generate periodic interrupts. Each timer can be independently set to operate in one of three modes: * Pulse Waveform Generation mode * Pulsewidth Count/Capture mode * External Event Watchdog mode Each timer has one bidirectional pin and four registers that implement its mode of operation: A 7-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulsewidth register. A single status register supports all three timers. A bit in each timer's configuration register enables or disables the corresponding timer independently of the others.
Memory Architecture
internal and external memory space, the ADSP-2191M can address two additional and separate off-chip memory spaces: I/O space and boot space. As shown in Figure 2, the DSP's two internal memory blocks populate all of Page 0. The entire DSP memory map consists of 256 pages (Pages 0-255), and each page is 64K words long. External memory space consists of four memory banks (banks 0-3) and supports a wide variety of SRAM memory devices. Each bank is selectable using the memory select pins (MS3-0) and has configurable page boundaries, waitstates, and waitstate modes. The 1K word of on-chip boot-ROM populates the top of Page 255 while the remaining 254 pages are addressable off-chip. I/O memory pages differ from external memory pages in that I/O pages are 1K word long, and the external I/O pages have their own select pin (IOMS). Pages 0-7 of I/O memory space reside on-chip and contain the configuration registers for the peripherals. Both the core and DMA-capable peripherals can access the DSP's entire memory map.
The ADSP-2191M DSP provides 64K words of on-chip SRAM memory. This memory is divided into four 16K blocks located on memory Page 0 in the DSP's memory map. In addition to the
64K WORD MEMORY PAGES INTERNAL MEMORY RESERVED PAGE 255 BOOT ROM, 24-BIT
LOGICAL ADDRESS 0 FF FFFF 0 FF 0400 0 FF 03FF 0 FF 0000
LOWER PAGE BOUNDARIES ARE CONFIGURABLE FOR BANKS OF EXTERNAL MEMORY. BOUNDARIES SHOWN ARE BANK SIZES AT RESET.
MEMORY SELECTS (MS) FOR PORTIONS OF THE MEMORY MAP APPEAR WITH THE SELECTED MEMORY.
PAGES 192-254
BANK3 (MS3) 0 C0 0000 BANK2 (MS2) 0 80 0000 BANK1 (MS1) 0 40 0000 BANK0 (MS0) 0 01 0000 BLOCK3, 16-BIT 0 00 C000 0 00 8000 0 00 4000 0 00 0000 8-BIT 10-BIT INTERNAL PAGES 1-254 0 FF 3FF 0 01 0000 EXTERNAL (IOMS) 0 08 000 0 07 3FF 0 00 000
PAGES 128-191 EXTERNAL MEMORY (16- BIT) PAGES 64-127
BOOT MEMORY 16-BIT (BMS) 64K WORD LOGICAL ADDRESS 0 FE FFFF
I/O MEMORY 16- BIT 1K WORD PAGES 8-255 1K WORD PAGES 0-7 LOGICAL ADDRESS
PAGES 1-63
INTERNAL MEMORY
BLOCK2, 16-BIT PAGE 0 BLOCK1, 24-BIT BLOCK0, 24-BIT
Figure 2. Memory Map Internal (On-Chip) Memory
The ADSP-2191M's unified program and data memory space consists of 16M locations that are accessible through two 24-bit address buses, the PMA and DMA buses. The DSP uses slightly
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ADSP-2191M
different mechanisms to generate a 24-bit address for each bus. The DSP has three functions that support access to the full memory map. * The DAGs generate 24-bit addresses for data fetches from the entire DSP memory address range. Because DAG index (address) registers are 16 bits wide and hold the lower 16 bits of the address, each of the DAGs has its own 8-bit page register (DMPGx) to hold the most significant eight address bits. Before a DAG generates an address, the program must set the DAG's DMPGx register to the appropriate memory page. * The Program Sequencer generates the addresses for instruction fetches. For relative addressing instructions, the program sequencer bases addresses for relative jumps, calls, and loops on the 24-bit Program Counter (PC). In direct addressing instructions (two-word instructions), the instruction provides an immediate 24-bit address value. The PC allows linear addressing of the full 24-bit address range. * For indirect jumps and calls that use a 16-bit DAG address register for part of the branch address, the Program Sequencer relies on an 8-bit Indirect Jump page (IJPG) register to supply the most significant eight address bits. Before a cross page jump or call, the program must set the program sequencer's IJPG register to the appropriate memory page. The ADSP-2191M has 1K word of on-chip ROM that holds boot routines. If peripheral booting is selected, the DSP starts executing instructions from the on-chip boot ROM, which starts the boot process from the selected peripheral. For more information, see "Booting Modes" on page 11. The on-chip boot ROM is located on Page 255 in the DSP's memory space map.
External (Off-Chip) Memory External Memory Space
External memory space consists of four memory banks. These banks can contain a configurable number of 64K word pages. At reset, the page boundaries for external memory have Bank0 containing pages 1-63, Bank1 containing pages 64-127, Bank2 containing pages 128-191, and Bank3 that contains pages 192-254. The MS3-0 memory bank pins select Banks 3-0, respectively. The external memory interface is byte-addressable and decodes the 8 MSBs of the DSP program address to select one of the four banks. Both the ADSP-219x core and DMA-capable peripherals can access the DSP's external memory space.
I/O Memory Space
The ADSP-2191M supports an additional external memory called I/O memory space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports a total of 256K locations. The first 8K addresses are reserved for on-chip peripherals. The upper 248K addresses are available for external peripheral devices. The DSP's instruction set provides instructions for accessing I/O space. These instructions use an 18-bit address that is assembled from an 8-bit I/O page (IOPG) register and a 10-bit immediate value supplied in the instruction. Both the ADSP-219x core and a Host (through the Host Port Interface) can access I/O memory space.
Boot Memory Space
Boot memory space consists of one off-chip bank with 63 pages. The BMS memory bank pin selects boot memory space. Both the ADSP-219x core and DMA-capable peripherals can access the DSP's off-chip boot memory space. After reset, the DSP always starts executing instructions from the on-chip boot ROM. Depending on the boot configuration, the boot ROM code can start booting the DSP from boot memory. For more information, see "Booting Modes" on page 11.
Interrupts
Each of the ADSP-2191M's off-chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. The access parameters include read and write wait counts, waitstate completion mode, I/O clock divide ratio, write hold time extension, strobe polarity, and data bus width. The core clock and peripheral clock ratios influence the external memory access strobe widths. For more information, see "Clock Signals" on page 11. The off-chip memory spaces are: * External memory space (MS3-0 pins) * I/O memory space (IOMS pin) * Boot memory space (BMS pin) All of these off-chip memory spaces are accessible through the External Port, which can be configured for data widths of 8 or 16 bits.
The interrupt controller lets the DSP respond to 17 interrupts with minimum overhead. The controller implements an interrupt priority scheme as shown in Table 1. Applications can use the unassigned slots for software and peripheral interrupts. Table 2 shows the ID and priority at reset of each of the peripheral interrupts. To assign the peripheral interrupts a different priority, applications write the new priority to their corresponding control bits (determined by their ID) in the Interrupt Priority Control register. The peripheral interrupt's position in the IMASK and IRPTL register and its vector address depend on its priority level, as shown in Table 1. Because the IMASK and IRPTL registers are limited to 16 bits, any peripheral interrupts
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assigned a priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x00 01E0.
Table 1. Interrupt Priorities/Addresses Interrupt IMASK/ IRPTL Vector Address1
The Interrupt Control (ICNTL) register controls interrupt nesting and enables or disables interrupts globally. The general-purpose Programmable Flag (PFx) pins can be configured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. Programmable Flag pin interrupts can be configured for level-sensitive, single edge-sensitive, or dual edge-sensitive operation.
Table 3. Interrupt Control (ICNTL) Register Bits Bit Description
Emulator (NMI)-- Highest Priority Reset (NMI) Power-Down (NMI) Loop and PC Stack Emulation Kernel User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt-- Lowest Priority
1These
NA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NA 0x00 0000 0x00 0020 0x00 0040 0x00 0060 0x00 0080 0x00 00A0 0x00 00C0 0x00 00E0 0x00 0100 0x00 0120 0x00 0140 0x00 0160 0x00 0180 0x00 01A0 0x00 01C0 0x00 01E0
0-3 4 5 6 7 8-9 10 11 12-15
Reserved Interrupt Nesting Enable Global Interrupt Enable Reserved MAC-Biased Rounding Enable Reserved PC Stack Interrupt Enable Loop Stack Interrupt Enable Reserved
interrupt vectors start at address 0x10000 when the DSP is in "no-boot," run from external memory mode.
The IRPTL register is used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. To support interrupt, loop, and subroutine nesting, the PC stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. To prevent stack overflow, the PC stack can generate a stack-level interrupt if the PC stack falls below three locations full or rises above 28 locations full. The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK.
ENA INT; DIS INT;
Table 2. Peripheral Interrupts and Priority at Reset Interrupt ID Reset Priority
Slave DMA/Host Port Interface SPORT0 Receive SPORT0 Transmit SPORT1 Receive SPORT1 Transmit SPORT2 Receive/SPI0 SPORT2 Transmit/SPI1 UART Receive UART Transmit Timer 0 Timer 1 Timer 2 Programmable Flag A (any PFx) Programmable Flag B (any PFx) Memory DMA port
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0 1 2 3 4 5 6 7 8 9 10 11 11 11 11
At reset, interrupt servicing is disabled. For quick servicing of interrupts, a secondary set of DAG and computational registers exist. Switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the DSP's state.
DMA Controller
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The emulation, power-down, and reset interrupts are nonmaskable with the IMASK register, but software can use the DIS INT instruction to mask the power-down interrupt. REV. 0 -7-
The ADSP-2191M has a DMA controller that supports automated data transfers with minimal overhead for the DSP core. Cycle stealing DMA transfers can occur between the ADSP-2191M's internal memory and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interface. DMA-capable peripherals include the Host port, SPORTs, SPI ports, and UART. Each individual DMA-capable peripheral has a dedicated DMA channel. To describe each DMA sequence, the DMA controller uses a set of parameters--called a DMA descriptor. When successive DMA sequences are needed, these DMA descriptors can be linked or chained together, so the completion of one DMA sequence auto-initiates and starts the next sequence. DMA sequences do not contend for bus access with the DSP core; instead DMAs "steal" cycles to access memory.
ADSP-2191M
All DMA transfers use the DMA bus shown in the functional block diagram on page 1. Because all of the peripherals use the same bus, arbitration for DMA bus access is needed. The arbitration for DMA bus access appears in Table 4.
Table 4. I/O Bus Arbitration Priority DMA Bus Master Arbitration Priority
The DSP uses HACK to indicate to the Host when to complete an access. For a read transaction, a Host can proceed and complete an access when valid data is present in the read buffer and the Host port is not busy doing a write. For a write transactions, a Host can complete an access when the write buffer is not full and the Host port is not busy doing a write. Two mode bits in the Host Port configuration register HPCR [7:6] define the functionality of the HACK line. HPCR6 is initialized at reset based on the values driven on HACK and HACK_P pins (shown in Table 5); HPCR7 is always cleared (0) at reset. HPCR [7:6] can be modified after reset by a write access to the Host port configuration register.
Table 5. Host Port Acknowledge Mode Selection Values Driven At Reset HACK_P HACK HPCR [7:6] Initial Values Bit 7 Bit 6
SPORT0 Receive DMA SPORT1 Receive DMA SPORT2 Receive DMA SPORT0 Transmit DMA SPORT1 Transmit DMA SPORT2 Transmit DMA SPI0 Receive/Transmit DMA SPI1 Receive/Transmit DMA UART Receive DMA UART Transmit DMA Host Port DMA Memory DMA
Host Port
0--Highest 1 2 3 4 5 6 7 8 9 10 11--Lowest
Acknowledge Mode
The ADSP-2191M's Host port functions as a slave on the external bus of an external Host. The Host port interface lets a Host read from or write to the DSP's memory space, boot space, or internal I/O space. Examples of Hosts include external microcontrollers, microprocessors, or ASICs. The Host port is a multiplexed address and data bus that provides both an 8-bit and a 16-bit data path and operates using an asynchronous transmission protocol. Through this port, an off-chip Host can directly access the DSP's entire memory space map, boot memory space, and internal I/O space. To access the DSP's internal memory space, a Host steals one cycle per access from the DSP. A Host access to the DSP's external memory uses the external port interface and does not stall (or steal cycles from) the DSP's core. Because a Host can access internal I/O memory space, a Host can control any of the DSP's I/O mapped peripherals. The Host port is most efficient when using the DSP as a slave and uses DMA to automate the incrementing of addresses for these accesses. In this case, an address does not have to be transferred from the Host for every data transfer.
Host Port Acknowledge (HACK) Modes
0 0 1 1
0 1 0 1
0 0 0 0
1 0 0 1
Ready Mode ACK Mode ACK Mode Ready Mode
The functional modes selected by HPCR [7:6] are as follows (assuming active high signal): * ACK Mode--Acknowledge is active on strobes; HACK goes high from the leading edge of the strobe to indicate when the access can complete. After the Host samples the HACK active, it can complete the access by removing the strobe.The Host port then removes the HACK. * Ready Mode--Ready active on strobes, goes low to insert waitstate during the access.If the Host port cannot complete the access, it deasserts the HACK/READY line. In this case, the Host has to extend the access by keeping the strobe asserted. When the Host samples the HACK asserted, it can then proceed and complete the access by deasserting the strobe. While in Address Cycle Control (ACC) mode and the ACK or Ready acknowledge modes, the HACK is returned active for any address cycle.
Host Port Chip Selects
The Host port supports a number of modes (or protocols) for generating a HACK output for the host. The host selects ACK or Ready Modes using the HACK_P and HACK pins. The Host port also supports two modes for address control: Address Latch Enable (ALE) and Address Cycle Control (ACC) modes. The DSP auto-detects ALE versus ACC Mode from the HALE and HWR inputs. The Host port HACK signal polarity is selected (only at reset) as active high or active low, depending on the value driven on the HACK_P pin.The HACK polarity is stored into the Host port configuration register as a read only bit.
There are two chip-select signals associated with the Host port: HCMS and HCIOMS. The Host Chip Memory Select (HCMS) lets the Host select the DSP and directly access the DSP's internal/external memory space or boot memory space. The Host Chip I/O Memory Select (HCIOMS) lets the Host select the DSP and directly access the DSP's internal I/O memory space. Before starting a direct access, the Host configures Host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target address page (in the IJPG register). The DSP generates the needed memory select signals during the access, based on the target address. The Host port interface combines the data from one, two, or three consecutive Host accesses (up to one 24-bit value) into a single DMA bus access to prefetch Host direct reads or to post direct writes. During assembly of larger words, the Host port interface asserts ACK for -8- REV. 0
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each byte access that does not start a read or complete a write. Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully.
DSP Serial Ports (SPORTs)
The ADSP-2191M incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the following features: * Bidirectional operation--each SPORT has independent transmit and receive pins. * Double-buffered transmit and receive ports--each port has a data register for transferring data words to and from memory and shift registers for shifting data in and out of the data registers. * Clocking--each transmit and receive port can either use an external serial clock (40 MHz) or generate its own, in frequencies ranging from 19 Hz to 40 MHz. * Word length--each SPORT supports serial data words from 3 to 16 bits in length transferred in Big Endian (MSB) or Little Endian (LSB) format. * Framing--each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. * Companding in hardware--each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead--each SPORT can automatically receive and transmit multiple buffers of memory data, one data word each DSP cycle. Either the DSP's core or a Host processor can link or chain sequences of DMA transfers between a SPORT and memory. The chained DMA can be dynamically allocated and updated through the DMA descriptors (DMA transfer parameters) that set up the chain. * Interrupts--each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability--each SPORT supports the H.100 standard.
Serial Peripheral Interface (SPI) Ports
SCKx). Two SPI chip select input pins (SPISSx) let other SPI devices select the DSP, and fourteen SPI chip select output pins (SPIxSEL7-1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI ports provide a full duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. Each SPI port's baud rate and clock phase/polarities are programmable (see equation below for SPI clock rate calculation), and each has an integrated DMA controller, configurable to support both transmit and receive data streams. The SPI's DMA controller can only service unidirectional accesses at any given time.
HCLK SPI Clock Rate = -------------------------------------2 x SPIBAUD
During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART Port
The UART port provides a simplified UART interface to another peripheral or Host. It performs full duplex, asynchronous transfers of serial data. Options for the UART include support for 5-8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART port supports two modes of operation: * Programmed I/O The DSP's core sends or receives data by writing or reading I/O-mapped THR or RBR registers, respectively. The data is double-buffered on both transmit and receive. * DMA (direct memory access) The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels. These DMA channels have lower priority than most DMA channels because of their relatively low service rates. The UART's baud rate (see following equation for UART clock rate calculation), serial data format, error code generation and status, and interrupts are programmable: * Supported bit rates range from 9.5 bits to 5M bits per second (80 MHz peripheral clock). * Supported data formats are 7- to 12-bit frames. * Transmit and receive status can be configured to generate maskable interrupts to the DSP's core. The timers can be used to provide a hardware-assisted autobaud detection mechanism for the UART interface.
HCLK UART Clock Rate = ----------------16 x D
The DSP has two SPI-compatible ports that enable the DSP to communicate with multiple SPI-compatible devices. These ports are multiplexed with SPORT2, so either SPORT2 or the SPI ports are active, depending on the state of the OPMODE pin during hardware reset. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input-Slave Output, MISOx) and a clock pin (Serial Clock,
Where D is the programmable divisor = 1 to 65536.
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Programmable Flag (PFx) Pins Idle Mode
The ADSP-2191M has 16 bidirectional, general-purpose I/O, Programmable Flag (PF15-0) pins. The PF7-0 pins are dedicated to general-purpose I/O. The PF15-8 pins serve either as general-purpose I/O pins (if the DSP is connected to an 8-bit external data bus) or serve as DATA15-8 lines (if the DSP is connected to a 16-bit external data bus). The Programmable Flag pins have special functions for clock multiplier selection and for SPI port operation. For more information, see Serial Peripheral Interface (SPI) Ports on page 9 and Clock Signals on page 11. Ten memory-mapped registers control operation of the Programmable Flag pins: * Flag Direction register Specifies the direction of each individual PFx pin as input or output. * Flag Control and Status registers Specify the value to drive on each individual PFx output pin. As input, software can predicate instruction execution on the value of individual PFx input pins captured in this register. One register sets bits, and one register clears bits. * Flag Interrupt Mask registers Enable and disable each individual PFx pin to function as an interrupt to the DSP's core. One register sets bits to enable interrupt function, and one register clears bits to disable interrupt function. Input PFx pins function as hardware interrupts, and output PFx pins function as software interrupts--latching in the IMASK and IRPTL registers. * Flag Interrupt Polarity register Specifies the polarity (active high or low) for interrupt sensitivity on each individual PFx pin. * Flag Sensitivity registers Specify whether individual PFx pins are level- or edge-sensitive and specify--if edge-sensitive--whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
Low Power Operation
When the ADSP-2191M is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. To enter Idle mode, the DSP can execute the IDLE instruction anywhere in code. To exit Idle mode, the DSP responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the IDLE.
Power-Down Core Mode
When the ADSP-2191M is in Power-Down Core mode, the DSP core clock is off, but the DSP retains the contents of the pipeline and keeps the PLL running. The peripheral bus keeps running, letting the peripherals receive data. To enter Power-Down Core mode, the DSP executes an IDLE instruction after performing the following tasks: * Enter a power-down interrupt service routine * Check for pending interrupts and I/O service routines * Clear (= 0) the PDWN bit in the PLLCTL register * Clear (= 0) the STOPALL bit in the PLLCTL register * Set (= 1) the STOPCK bit in the PLLCTL register To exit Power-Down Core mode, the DSP responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the IDLE.
Power-Down Core/Peripherals Mode
When the ADSP-2191M is in Power-Down Core/Peripherals mode, the DSP core clock and peripheral bus clock are off, but the DSP keeps the PLL running. The DSP does not retain the contents of the instruction pipeline.The peripheral bus is stopped, so the peripherals cannot receive data. To enter Power-Down Core/Peripherals mode, the DSP executes an IDLE instruction after performing the following tasks: * Enter a power-down interrupt service routine * Check for pending interrupts and I/O service routines * Clear (= 0) the PDWN bit in the PLLCTL register * Set (= 1) the STOPALL bit in the PLLCTL register To exit Power-Down Core/Peripherals mode, the DSP responds to a wake-up event and (after five to six cycles of latency) resumes executing instructions with the instruction after the IDLE.
Power-Down All Mode
The ADSP-2191M has four low-power options that significantly reduce the power dissipation when the device operates under standby conditions. To enter any of these modes, the DSP executes an IDLE instruction. The ADSP-2191M uses configuration of the PDWN, STOPCK, and STOPALL bits in the PLLCTL register to select between the low-power modes as the DSP executes the IDLE. Depending on the mode, an IDLE shuts off clocks to different parts of the DSP in the different modes. The low power modes are: * Idle * Power-Down Core * Power-Down Core/Peripherals * Power-Down All
When the ADSP-2191M is in Power-Down All mode, the DSP core clock, the peripheral clock, and the PLL are all stopped. The DSP does not retain the contents of the instruction pipeline. The peripheral bus is stopped, so the peripherals cannot receive data. To enter Power-Down All mode, the DSP executes an IDLE instruction after performing the following tasks: * Enter a power-down interrupt service routine * Check for pending interrupts and I/O service routines * Set (= 1) the PDWN bit in the PLLCTL register
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To exit Power-Down Core/Peripherals mode, the DSP responds to an interrupt and (after 500 cycles to restabilize the PLL) resumes executing instructions with the instruction after the IDLE.
Clock Signals
1M
25MHz CLKIN MSEL0 (PF0) XTAL CLKOUT
The ADSP-2191M can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. If a crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors and a 1 M shunt resistor connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used for this configuration. If a buffered, shaped clock is used, this external clock connects to the DSP's CLKIN pin. CLKIN input cannot be halted, changed, or operated below the specified frequency during normal operation. When an external clock is used, the XTAL input must be left unconnected. The DSP provides a user-programmable 1 to 32 multiplication of the input clock, including some fractional values, to support 128 external to internal (DSP core) clock ratios. The MSEL6-0, BYPASS, and DF pins decide the PLL multiplication factor at reset. At runtime, the multiplication factor can be controlled in software. The combination of pullup and pull-down resistors in Figure sets up a core clock ratio of 6:1, which produces a 150 MHz core clock from the 25 MHz input. For other clock multiplier settings, see the ADSP-219x/2191 DSP Hardware Reference. The peripheral clock is supplied to the CLKOUT pin. All on-chip peripherals for the ADSP-2191M operate at the rate set by the peripheral clock. The peripheral clock is either equal to the core clock rate or one-half the DSP core clock rate. This selection is controlled by the IOSEL bit in the PLLCTL register. The maximum core clock is 160 MHz and the maximum peripheral clock is 80 MHz--the combination of the input clock and core/peripheral clock ratios may not exceed these limits.
Reset
VDD
ADSP-2191M
MSEL1 (PF1)
VDD
MSEL2 (PF2) RUNTIME PF PIN I/O
MSEL3 (PF3)
MSEL4 (PF4)
MSEL5 (PF5) THE PULL-UP/PULL-DOWN RESISTORS ON THE MSEL, DF, AND BYPASS PINS SELECT THE CORE CLOCK RATIO. HERE, THE SELECTION (6:1) AND 25MHz INPUT CLOCK PRODUCE A 150MHz CORE CLOCK.
MSEL6 (PF6)
DF (PF7)
BYPASS
RESET SOURCE
RESET
Figure 3. External Crystal Connections
The RESET input contains some hysteresis. If using an RC circuit to generate your RESET signal, the circuit should use an external Schmidt trigger. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. Program control jumps to the location of the on-chip boot ROM (0xFF 0000).
Power Supplies
The RESET signal initiates a master reset of the ADSP-2191M. The RESET signal must be asserted during the powerup sequence to assure proper initialization. RESET during initial powerup must be held long enough to allow the internal clock to stabilize. The powerup sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 100 s ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this powerup sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tWRST.
The ADSP-2191M has separate power supply connections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 2.5 V requirement. The external supply must be connected to a 3.3 V supply. All external supply pins must be connected to the same supply.
Powerup Sequence
Power up together the two supplies VDDEXT and VDDINT. If they cannot be powered up together, power up the internal (core) supply first (powering up the core supply first reduces the risk of latchup events.
Booting Modes
The ADSP-2191M has five mechanisms (listed in Table 6) for automatically loading internal program memory after reset. Two No-boot modes are also supported.
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Table 6. Select Boot Mode (OPMODE, BMODE1, and BMODE0) OPMODE BMODE1 BMODE0
* Execute from memory external 8 bits (No Boot)-- Execution starts from Page 1 of external memory space, packing either 8- or 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (128) and read waitstates (7). * Boot from UART--The Host downloads boot-stream-formatted program using an autobaud handshake sequence. The Host agent selects a baud rate within the UART's clocking capabilities. After a hardware reset, the DSP's UART expects a 0xAA character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate; and then replies with an OK string. Once the host receives this OK it downloads the boot stream without further handshake.The UART boot routine is located in internal ROM memory space and uses the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory. * Boot from SPI, up to 4K bits--The SPI0 port uses the SPI0SEL1 (reconfigured PF2) output pin to select a single serial EEPROM device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. Use only SPI-compatible EEPROMs of 4K bit (12-bit address range). The SPI0 boot routine located in internal ROM memory space executes a boot-stream-formatted program, using the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory. The SPI boot configuration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1, 8-bit data, and MSB first. * Boot from SPI, from >4K bits to 512K bits--The SPI0 port uses the SPI0SEL1 (re-configured PF2) output pin to select a single serial EEPROM device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. Use only SPI-compatible EEPROMs of 4K bit (16-bit address range). The SPI0 boot routine, located in internal ROM memory space, executes a boot-stream-formatted program, using the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory. As indicated in Table 6, the OPMODE pin has a dual role, acting as a boot mode select during reset and determining SPORT or SPI operation at runtime. If the OPMODE pin at reset is the opposite of what is needed in an application during runtime, the application needs to set the OPMODE bit appropriately during runtime prior to using the corresponding peripheral.
Bus Request and Bus Grant
Function
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Execute from external memory 16 bits (No Boot) Boot from EPROM Boot from Host Reserved Execute from external memory 8 bits (No Boot) Boot from UART Boot from SPI, up to 4K bits Boot from SPI, >4K bits up to 512K bits
The OPMODE, BMODE1, and BMODE0 pins, sampled during hardware reset, and three bits in the Reset Configuration Register implement these modes: * Execute from memory external 16 bits--The memory boot routine located in boot ROM memory space executes a boot-stream-formatted program located at address 0x010000 of boot memory space, packing 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (128) and read waitstates (7). * Boot from EPROM--The EPROM boot routine located in boot ROM memory space fetches a boot-stream-formatted program located at physical address 0x00 0000 of boot memory space, packing 8- or 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (32) and read waitstates (7). * Boot from Host--The (8- or 16-bit) Host downloads a boot-stream-formatted program to internal or external memory. The Host's boot routine is located in internal ROM memory space and uses the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory. The internal boot ROM sets semaphore A (an IO register within the Host port) and then polls until the semaphore is reset. Once detected, the internal boot ROM will remap the interrupt vector table to Page 0 internal memory and jump to address 0x00 0000 internal memory. From the point of view of the host interface, an external host has full control of the DSP's memory map. The Host has the freedom to directly write internal memory, external memory, and internal I/O memory space. The DSP core execution is held off until the Host clears the semaphore register. This strategy allows the maximum flexibility for the Host to boot in the program and data code, by leaving it up to the programmer.
The ADSP-2191M can relinquish control of the data and address buses to an external device. When the external device requires access to the bus, it asserts the bus request (BR) signal. The (BR) signal is arbitrated with core and peripheral requests. External Bus requests have the lowest priority. If no other internal request is pending, the external bus request will be granted. Because of
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synchronizer and arbitration delays, bus grants will be provided with a minimum of three peripheral clock delays. ADSP-2191M DSPs will respond to the bus grant by: * Three-stating the data and address buses and the MS3-0, BMS, IOMS, RD, and WR output drivers. * Asserting the bus grant (BG) signal. The ADSP-2191M will halt program execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to external general-purpose or peripheral memory spaces. If an instruction requires two external memory read accesses, bus requests will not be granted between the two accesses. If an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. The external memory interface can be configured so that the core will have exclusive use of the interface. DMA and Bus Requests will be granted. When the external device releases BR, the DSP releases BG and continues program execution from the point at which it stopped. The bus request feature operates at all times, even while the DSP is booting and RESET is active. The ADSP-2191M asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems.
Instruction Set Description Development Tools
The ADSP-2191M is supported with a complete set of software and hardware development tools, including Analog Devices emulators and VisualDSP++(R) development environment. The same emulator hardware that supports other ADSP-219x DSPs, also fully emulates the ADSP-2191M. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. Two key points for these tools are: * Compiled ADSP-219x C/C++ code efficiency--the compiler has been developed for efficient translation of C/C++ code to ADSP-219x assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. * ADSP-218x family code compatibility--The assembler has legacy features to ease the conversion of existing ADSP-218x applications to the ADSP-219x. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert break points * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Source level debugging * Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the ADSP-219x development tools, including the syntax highlighting in the VisualDSP++ editor. This capability permits: * Control how the development tools process inputs and generate outputs. * Maintain a one-to-one correspondence with the tool's command line switches. Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-2191M processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing.
The ADSP-2191M assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * ADSP-219x assembly language syntax is a superset of and source-code-compatible (except for two data registers and DAG base address registers) with ADSP-218x family syntax. It may be necessary to restructure ADSP-218x programs to accommodate the ADSP-2191M's unified memory space and to conform to its interrupt vector map. * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction, but two, assembles into a single, 24-bit word that can execute in a single instruction cycle. The exceptions are two dual word instructions. One writes 16or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24-bit address specified in the instruction. * Multifunction instructions allow parallel execution of an arithmetic, MAC, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle. * Program flow instructions support a wider variety of conditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions. REV. 0
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In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-219x processor family. Hardware tools include ADSP-219x PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
As can be seen in Figure 4, there are two sets of signals on the header. There are the standard JTAG signals TMS, TCK, TDI, TDO, TRST, and EMU used for emulation purposes (via an emulator). There are also secondary JTAG signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing. When the emulator is not connected to this header, place jumpers across BTMS, BTCK, BTRST, and BTDI as shown in Figure 5. This holds the JTAG signals in the correct state to allow the DSP to run free. Remove all the jumpers when connecting the emulator to the JTAG header.
The White Mountain DSP (Product Line of Analog Devices, Inc.) family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target's design must include the interface between an Analog Devices JTAG DSP and the emulation header on a custom DSP target board.
Target Board Header
GND
1
2
EMU
3 KEY (NO PIN) 5 BTMS 7 BTCK BTRST 9 9 11 BTDI 13
4 GND 6 TMS 8 TCK 10 TRST
12 TDI 14
The emulator interface to an Analog Devices JTAG DSP is a 14-pin header, as shown in Figure 4. The customer must supply this header on the target board in order to communicate with the emulator. The interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". Pin 3 is the key position used to prevent the pod from being inserted backwards. This pin must be clipped on the target board. Also, the clearance (length, width, and height) around the header must be considered. Leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector.
GND
TDO
TOP VIEW
Figure 5. JTAG Target Board Connector with No Local Boundary Scan JTAG Emulator Pod Connector
1 GND 3 KEY (NO PIN) 5 BTMS 7 BTCK 9 BTRST 11 BTDI 13 GND 9
2
EMU
Figure 6 details the dimensions of the JTAG pod connector at the 14-pin target end. Figure 7 displays the keep-out area for a target board header. The keep-out area allows the pod connector to properly seat onto the target board header. This board area should contain no components (chips, resistors, capacitors, etc.). The dimensions are referenced to the center of the 0.25" square post pin.
4 GND 6 TMS 8 TCK 10 TRST
0.64"
12 TDI 14 TDO
TOP VIEW
0.88" 0.24"
Figure 4. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
Figure 6. JTAG Pod Connector Dimensions
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Additional Information
0.10"
This data sheet provides a general overview of the ADSP-2191M architecture and functionality. For detailed information on the core architecture of the ADSP-219x family, refer to the ADSP-219x/2191 DSP Hardware Reference. For details on the instruction set, refer to the ADSP-219x Instruction Set Reference.
PIN FUNCTION DESCRIPTIONS
0.15"
Figure 7. JTAG Pod Connector Keep-Out Area Design-for-Emulation Circuit Information
For details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)--use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support.
ADSP-2191M pin definitions are listed in Table 7. All ADSP-2191M inputs are asynchronous and can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for ADDR21-0, DATA15-0, PF7-0, and inputs that have internal pull-up or pull-down resistors (TRST, BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, and RESET)--these pins can be left floating. These pins have a logic-level hold circuit that prevents input from floating internally. The following symbols appear in the Type column of Table : G = Ground, I = Input, O = Output, P = Power Supply, and T = Three-State.
Table 7. Pin Function Descriptions Pin Type Function
A21-0 D7-0 D15 /PF15 /SPI1SEL7 D14 /PF14 /SPI0SEL7 D13 /PF12 /SPI1SEL6 D12 /PF12 /SPI0SEL6 D11 /PF11 /SPI1SEL5 D10 /PF10 /SPI0SEL5 D9 /PF9 /SPI1SEL4 D8 /PF8 /SPI0SEL4 PF7 /SPI1SEL3 /DF PF6 /SPI0SEL3 /MSEL6
O/T I/O/T I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I I I/O/T I I
External Port Address Bus External Port Data Bus, least significant 8 bits Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave Select output 7 (if 8-bit external bus, when SPI1 enabled) Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave Select output 7 (if 8-bit external bus, when SPI0 enabled) Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave Select output 6 (if 8-bit external bus, when SPI1 enabled) Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave Select output 6 (if 8-bit external bus, when SPI0 enabled) Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave Select output 5 (if 8-bit external bus, when SPI1 enabled) Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave Select output 5 (if 8-bit external bus, when SPI0 enabled) Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select output 4 (if 8-bit external bus, when SPI1 enabled) Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select output 4 (if 8-bit external bus, when SPI0 enabled) Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency (divisor select for PLL input during boot) Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6 (during boot)
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Table 7. Pin Function Descriptions (continued) Pin Type Function
PF5 /SPI1SEL2 /MSEL5 PF4 /SPI0SEL2 /MSEL4 PF3 /SPI1SEL1 /MSEL3 PF2 /SPI0SEL1 /MSEL2 PF1 /SPISS1 /MSEL1 PF0 /SPISS0 /MSEL0 RD WR ACK BMS IOMS MS3-0 BR BG BGH HAD15-0 HA16 HACK_P HRD HWR HACK HALE HCMS HCIOMS CLKIN XTAL BMODE1-0 OPMODE CLKOUT BYPASS RCLK1-0 RCLK2/SCK1 RFS1-0 RFS2/MOSI1 TCLK1-0 TCLK2/SCK0 TFS1-0 TFS2/MOSI0 DR1-0 DR2/MISO1 DT1-0 DT2/MISO0 TMR2-0
I/O/T I I I/O/T I I I/O/T I I I/O/T I I I/O/T I I I/O/T I I O/T O/T I O/T O/T O/T I O O I/O/T I I I I O I I I I O I I O I I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/T I/O/T O/T I/O/T I/O/T
Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5 (during boot) Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4 (during boot) Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3 (during boot) Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2 (during boot) Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1 (during boot) Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0 (during boot) External Port Read Strobe External Port Write Strobe External Port Access Ready Acknowledge External Port Boot Space Select External Port IO Space Select External Port Memory Space Selects External Port Bus Request External Port Bus Grant External Port Bus Grant Hang Host Port Multiplexed Address and Data Bus Host Port MSB of Address Bus Host Port ACK Polarity Host Port Read Strobe Host Port Write Strobe Host Port Access Ready Acknowledge Host Port Address Latch Strobe or Address Cycle Control Host Port Internal Memory-Internal I/O Memory-Boot Memory Select Host Port Internal I/O Memory Select Clock Input/Oscillator input Oscillator output Boot Mode 1-0. The BMODE1 and BMODE0 pins have 85 k internal pull-up resistors. Operating Mode. The OPMODE pin has a 85 k internal pull-up resistor. Clock Output Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 k internal pull-up resistor. SPORT1-0 Receive Clock SPORT2 Receive Clock/SPI1 Serial Clock SPORT1-0 Receive Frame Sync SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data SPORT1-0 Transmit Clock SPORT2 Transmit Clock/SPI0 Serial Clock SPORT1-0 Transmit Frame Sync SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data SPORT1-0 Serial Data Receive SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data SPORT1-0 Serial Data Transmit SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data Timer output or capture -16- REV. 0
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Table 7. Pin Function Descriptions (continued) Pin Type Function
RXD TXD RESET
I O I
TCK TMS TDI TDO TRST
I I I O I
EMU VDDINT VDDEXT GND NC
O P P G
UART Serial Receive Data UART Serial Transmit Data Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at powerup. The RESET pin has an 85 k internal pull-up resistor. Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has an 85 k internal pull-up resistor. Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has an 85 k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a 85 k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-2191M. The TRST pin has a 65 k internal pull-down resistor. Emulation Status (JTAG). Must be connected to the ADSP-2191M emulator target board connector only. Core Power Supply. Nominally 2.5 V dc and supplies the DSP's core processor. (four pins) I/O Power Supply. Nominally 3.3 V dc. (nine pins) Power Supply Return. (twelve pins) Do Not Connect. Reserved pins that must be left open and unconnected.
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ADSP-2191M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
Parameter1 Test Conditions K Grade (Commercial) Min Max B Grade (Industrial) Min Max Unit
VDDINT VDDEXT VIH VIL TAMB
1Specifications
Internal (Core) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Operating Temperature
subject to change without notice.
2.37 2.97 @ VDDINT = max, 2.0 VDDEXT = max @ VDDINT = min, -0.3 VDDEXT = min 0
2.63 3.6
2.37 2.97
2.63 3.6
V V
VDDEXT +0.3 2.0 0.8 70 -0.3 -40
VDDEXT +0.3 V 0.8 +85 V C
ELECTRICAL CHARACTERISTICS
Parameter1 Test Conditions K and B Grades Min Typ Max Unit
VOH VOL IIH IIL IIHP IILP IOZH IOZL CIN
High Level Output
Voltage2
Low Level Output Voltage2 High Level Input Current3, 4 Low Level Input Current3, 5 High Level Input Current5 Low Level Input Current4 Three-State Leakage Current6 Three-State Leakage Current6 Input Capacitance7, 8
@ VDDEXT = min, IOH = -0.5 mA @ VDDEXT = min, IOL = 2.0 mA @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V fIN = 1 MHz, TCASE = 25C, VIN = 2.5 V
2.4 0.4 10 10 30 20 100 70 10 10 8
V V A A A A A A pF
1Specifications 2Applies
subject to change without notice. to output and bidirectional pins: DATA15-0, ADDR21-0, HAD15-0, MS3-0, IOMS, RD, WR, CLKOUT, HACK, PF7-0, TMR2-0, BGH, BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1. 3Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P. 4Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET. 5Applies to input pin with internal pull-down: TRST. 6 Applies to three-statable pins: DATA15-0, ADDR21-0, MS3-0, RD, WR, PF7-0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx, HAD15-0, TMR2-0. 7Applies to all signal pins. 8Guaranteed, but not tested.
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ABSOLUTE MAXIMUM RATINGS
VDDINT Internal (Core) Supply Voltage1,2. . -0.3 V to 3.0 V VDDEXT External (I/O) Supply Voltage . . . . -0.3 V to 4.6 V VIL-VIH Input Voltage . . . . . . . . -0.5 V to VDDEXT +0.5 V VOL-VOH Output Voltage Swing . -0.5 V to VDDEXT +0.5 V TSTOREStorage Temperature Range . . . . . . -65C to 150C TLEADLead Temperature of ST-144 (5 seconds) . . . . 185C
1Specifications 2
subject to change without notice. Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2191M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Power Dissipation
Using the operation-versus-current information in Table 8, designers can estimate the ADSP-2191M's internal power supply (VDDINT) input current for a specific application, according to the formula for IDDINT calculation beneath Table 8. For calculation of external supply current and total supply current, see Power Dissipation on page 41.
Table 8. Operation Types Versus Input Current K-Grade IDDINT(mA) CCLK = 160 MHz Core Activity Typ1 Max2 Peripheral Typ1 Max2 B-Grade IDDINT(mA)1 CCLK = 140 MHz Core Typ1 Max2 Peripheral Typ1 Max2
Power Down3 Idle 14 Idle 25 Typical6 Peak7
1Test 2Test
100A 1 1 184 215
600A 2 2 210 240
0 5 60 60 60
50A 8 70 70 70
100A 1 1 165 195
500A 2 2 185 210
0 4 55 55 55
50A 7 62 62 62
conditions: VDDINT= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25C. conditions: VDDINT= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25C. 3 PLL, Core, peripheral clocks, and CLKIN are disabled. 4PLL is enabled and Core and peripheral clocks are disabled. 5Core CLK is disabled and peripheral clock is enabled. 6All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using a linear address sequence. 50% of the instructions are type 3 instructions. 7All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear address sequence.
I DDINT = ( %Typical x I DDINT-TYPICAL ) + ( %Idle x I DDINT-IDLE ) + ( %Power Down x I DDINT-PWRDWN )
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ADSP-2191M TIMING SPECIFICATIONS
This section contains timing information for the DSP's external signals. Use the exact information given. Do not attempt to derive parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be added meaningfully to derive longer times. Switching characteristics specify how the processor changes its signals. No control is possible over this timing; circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation.Timing requirements guarantee that the processor operates correctly with other devices.
Clock In and Clock Out Cycle Timing
Table 9 and Figure 8 describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins. When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.
Table 9. Clock In and Clock Out Cycle Timing Parameter Min Max Unit
Switching Characteristics tCKOD CLKOUT Delay from CLKIN tCKO CLKOUT Period1 Timing Requirements CLKIN Period2, 3 tCK tCKL CLKIN Low Pulse tCKH CLKIN High Pulse tWRST RESET Asserted Pulsewidth Low tMSS MSELx/BYPASS Stable Before RESET Deasserted Setup MSELx/BYPASS Stable After RESET Deasserted Hold tMSH MSELx/BYPASS Stable After RESET Asserted tMSD Flag Output Disable Time After RESET Asserted tPFD
1CLKOUT 2In
0 12.5 10 4.5 4.5 200tCLKOUT 40 1000
5.8
ns ns ns ns ns ns s ns ns ns
200
200 10
jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns. clock multiplier mode and MSEL6-0 set for 1:1 (or CLKIN=CCLK), tCK=tCCLK. 3In bypass mode, t CK=tCCLK.
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tCK
CLKI N
tCKL
tCKH tW RST
RESET
tMSD tPFD
MSEL 6-0 B YPASS DF
tM SS
tMSH
tC K O D
CL KOU T
tC K O
Figure 8. Clock In and Clock Out Cycle Timing
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ADSP-2191M
Programmable Flags Cycle Timing
Table 10 and Figure 9 describe Programmable Flag operations.
Table 10. Programmable Flags Cycle Timing Parameter Min Max Unit
Switching Characteristics tDFO Flag Output Delay with Respect to CLKOUT tHFO Flag Output Hold After CLKOUT High Timing Requirement Flag Input Hold is asynchronous tHFI 3
7 6
ns ns ns
CLKOUT
tDFO
PF (OUTPUT)
tHFO
FLAG OUTPUT
tHFI
PF (INPUT) FLAG INPUT
Figure 9. Programmable Flags Cycle Timing Timer PWM_OUT Cycle Timing
Table 11 and Figure 10 describe timer expired operations. The input signal is asynchronous in "width capture mode" and has an absolute maximum input frequency of 40 MHz.
Table 11. Timer PWM_OUT Cycle Timing Parameter Min Max Unit
Switching Characteristic Timer Pulsewidth Output1 tHTO
1The
12.5
(232 -1) cycles
ns
minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232 -1) cycles.
HCLK
tHTO
P W M _OUT
Figure 10. Timer PWM_OUT Cycle Timing
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External Port Write Cycle Timing
Table 12 and Figure 11 describe external port write operations. The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-219x/2191 DSP Hardware Reference.
Table 12. External Port Write Cycle Timing Parameter1, 2 Min Max Unit
Switching Characteristics tCSWS Chip Select Asserted to WR Asserted Delay tAWS Address Valid to WR Setup and Delay tWSCS WR Deasserted to Chip Select Deasserted tWSA WR Deasserted to Address Invalid tWW WR Strobe Pulsewidth WR to Data Enable Access Delay tCDA tCDD WR to Data Disable Access Delay tDSW Data Valid to WR Deasserted Setup tDHW WR Deasserted to Data Invalid Hold Time; E_WHC4 tDHW WR Deasserted to Data Invalid Hold Time; E_WHC4 tWWR WR Deasserted to WR, RD Asserted Timing Requirements ACK Strobe Pulsewidth tAKW ACK Delay from WR Low tDWSAK
1t 3 HCLK is the peripheral clock period. 2These are timing parameters that are
0.5tHCLK -4 0.5tHCLK -3 0.5tHCLK -4 0.5tHCLK -3 tHCLK -2+W3 0.5tHCLK -3 tHCLK +1+W3 3.4 tHCLK +3.4 tHCLK 12.5 0 0 0.5tHCLK +4 tHCLK +7+W3
ns ns ns ns ns ns ns ns ns ns
ns ns
based on worst-case operating conditions. W = (number of waitstates specified in wait register) tHCLK. 4Write hold cycle-memory select control registers (MS CTL).
tCSW S
M S3-0 IO M S BMS
tW SCS
A21-0
tAW S
WR
tW W
tW SA
tDW SA K
ACK
tAKW
tW W R
tCDD tCDA tDSW tDHW
D15-0
RD
Figure 11. External Port Write Cycle Timing
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ADSP-2191M
External Port Read Cycle Timing
Table 13 and Figure 12 describe external port read operations. For additional information on the ACK signal, see the discussion on page 23.
Table 13. External Port Read Cycle Timing Parameter1, 2 Min Max Unit
Switching Characteristics tCSRS Chip Select Asserted to RD Asserted Delay Address Valid to RD Setup and Delay tARS tRSCS RD Deasserted to Chip Select Deasserted Setup tRW RD Strobe Pulsewidth tRSA RD Deasserted to Address Invalid Setup tRWR RD Deasserted to WR, RD Asserted Timing Requirements ACK Strobe Pulsewidth tAKW tRDA RD Asserted to Data Access Setup tADA Address Valid to Data Access Setup tSDA Chip Select Asserted to Data Access Setup tSD Data Valid to RD Deasserted Setup tHRD RD Deasserted to Data Invalid Hold ACK Delay from RD Low tDRSAK
1t HCLK is the peripheral clock period. 2These are timing parameters that are 3W
0.5tHCLK -3 0.5tHCLK -3 0.5tHCLK -2 tHCLK -2+W3 0.5tHCLK -2 tHCLK tHCLK
ns ns ns ns ns
tHCLK -4+W3 tHCLK +W3 tHCLK +W3
7 0 0
ns ns ns ns ns ns ns
based on worst-case operating conditions. = (number of waitstates specified in wait register) tHCLK.
MS3-0 IOMS BMS
tCSRS
tRSCS
A21-0
tARS
RD
tR W
tRSA
tDRSAK tAKW
ACK
tRW R
tCDA
tSD
tH R D
D15-0
tRDA tADA tSDA
WR
Figure 12. External Port Read Cycle Timing
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External Port Bus Request and Grant Cycle Timing
Table 14 and Figure 13 describe external port bus request and bus grant operations.
Table 14. External Port Bus Request and Grant Cycle Timing Parameter1, 2 Min Max Unit
Switching Characteristics tSD CLKOUT High to xMS, Address, and RD/WR Disable tSE CLKOUT Low to xMS, Address, and RD/WR Enable tDBG CLKOUT High to BG Asserted Setup CLKOUT High to BG Deasserted Hold Time tEBG tDBH CLKOUT High to BGH Asserted Setup tEBH CLKOUT High to BGH Deasserted Hold Time Timing Requirements tBS BR Asserted to CLKOUT High Setup tBH CLKOUT High to BR Deasserted Hold Time
1
0 0 0 0 0 4.6 0
0.5tHCLK +1 4 4 4 4 4
ns ns ns ns ns ns ns ns
tHCLK is the peripheral clock period. 2These are timing parameters that are
based on worst-case operating conditions.
CLK OUT
tBS
BR
tBH
tS D
MS3-0 IOMS BMS
tSE
tSD
tS E
A 21-0
tSD
WR RD
tSE
tDBG
tEBG
BG
tDBH
tE B H
BGH
Figure 13. External Port Bus Request and Grant Cycle Timing
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ADSP-2191M
Host Port ALE Mode Write Cycle Timing
Table 15 and Figure 14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 15. Host Port ALE Mode Write Cycle Timing Parameter Min Max Unit
Switching Characteristics tWHKS1 HWR Asserted to HACK Asserted (Setup, ACK Mode) First Byte HWR Asserted to HACK Asserted (Setup, ACK Mode)2 tWHKS2 tWHKH HWR Deasserted to HACK Deasserted (Hold, ACK Mode) tWHS tWHH HWR Asserted to HACK Asserted (Setup, Ready Mode) HWR Asserted to HACK Deasserted (Hold, Ready Mode) First Byte
10
5tHCLK +tNH1 10 10 10 5tHCLK +tNH1
ns ns ns ns ns
0
Timing Requirements HCMS or HCIOMS Asserted to HALE Asserted tCSAL tALPW HALE Asserted Pulsewidth tALCSW HALE Deasserted to HCMS or HCIOMS Deasserted tWCSW HWR Deasserted to HCMS or HCIOMS Deasserted tALW HALE Deasserted to HWR Asserted tWCS HWR Deasserted (After Last Byte) to HCMS or HCIOMS Deasserted (Ready for Next Write) HACK Asserted to HWR Deasserted (Hold, ACK Mode) tHKWD tAALS Address Valid to HALE Deasserted (Setup) tALAH HALE Deasserted to Address Invalid (Hold) tDWS Data Valid to HWR Deasserted (Setup) tWDH HWR Deasserted to Data Invalid (Hold)
1t NH are peripheral bus latencies (n
0 4 1 0 1 0 1.5 2 4 4 1
ns ns ns ns ns ns ns ns ns ns ns
t HCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory at the same time. 2Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
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H CMS HIO MS
t C SA L
HALE
tA LPW
tA LC SW t WC SW
tA LW
HWR
t WC S
t H K WD t WH K S
H ACK (ACK MO DE)
t WH KH
HA CK EACH BYT E
t WH H t WH S
HACK (READY M ODE) H AC K F IRST B YTE
tA LA H tA A LS
t D WS t WD H
HAD15-0 HA16
A DDR ESS VA LID STA RT F I RST W OR D
DA TA VAL ID FI RST BYT E
DAT A VA LID L AST BYT E
AD DR ESS VA LI D ST ART NEXT WO R D
Figure 14. Host Port ALE Mode Write Cycle Timing
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Host Port ACC Mode Write Cycle Timing
Table 16 and Figure 15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 16. Host Port ACC Mode Write Cycle Timing Parameter Min Max Unit
Switching Characteristics tWHKS1 HWR Asserted to HACK Asserted (ACK Mode) First Byte HWR Asserted to HACK Asserted (Setup, ACK Mode)2 tWHKS2 tWHKH HWR Deasserted to HACK Deasserted (Hold, ACK Mode) tWHS HWR Asserted to HACK Asserted (Setup, Ready Mode) tWHH HWR Asserted to HACK Deasserted (Hold, Ready Mode) First Byte HWR Asserted to HACK Asserted (Setup) During Address tWSHKS Latch HWR Deasserted to HACK Deasserted (Hold) During tWHHKH Address Latch Timing Requirements HWR Asserted to HALE Deasserted (Delay) tWAL tCSAL HCMS or HCIOMS Asserted to HALE Asserted (Delay) tALCS HALE Deasserted to Optional HCMS or HCIOMS Deasserted HWR Deasserted to HCMS or HCIOMS Deasserted tWCSW HALE Asserted to HWR Asserted tALW tCSW HCMS or HCIOMS Asserted to HWR Asserted tWCS HWR Deasserted (After Last Byte) to HCMS or HCIOMS Deasserted (Ready for Next Write) tALEW HALE Deasserted to HWR Asserted HACK Asserted to HWR Deasserted (Hold, ACK Mode) tHKWD tADW Address Valid to HWR Asserted (Setup) tWAD HWR Deasserted to Address Invalid (Hold) tDWS Data Valid to HWR Deasserted (Setup) tWDH HWR Deasserted to Data Invalid (Hold) HACK Asserted to HWR Deasserted (Hold) During Address tHKWAL Latch2
1t NH are peripheral bus latencies (n
10
0
5tHCLK +tNH1 12 10 10 5tHCLK +tNH1 10 10
ns ns ns ns ns ns ns
1.5 0 1 0 0.5 0 0 1 1.5 3 3 2 2 2
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory at the same time. 2 Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
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HCMS HIOMS
tA LC S t CS A L
H AL E
tWA L
t WC SW
t CS W t A LW
HWR
t ALE W
t WC S
t HKW A L t W S HK S
HACK ( ACK MO D E)
t H KW D t WH K H t W HK S
H AC K EAC H B YTE
t WH H KH
HACK (R EA DY M OD E)
t WH S
t WH H
H ACK FIR ST B YTE
t WA D t ADW
H A D15 -0 H A 16 A DDR ESS VA LI D ST AR T FI R ST WO RD
t D WS
DA TA VALI D F IRST B YTE
t WD H
D ATA VAL ID LA ST BYTE AD DR ESS VA LID S TAR T NEX T WORD
Figure 15. Host Port ACC Mode Write Cycle Timing
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Host Port ALE Mode Read Cycle Timing
Table 17 and Figure 16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 17. Host Port ALE Mode Read Cycle Timing Parameter Min Max Unit
Switching Characteristics tRHKS1 HRD Asserted to HACK Asserted (ACK Mode) First Byte HRD Asserted to HACK Asserted (Setup, ACK Mode)2 tRHKS2 tRHKH HRD Deasserted to HACK Deasserted (Hold, ACK Mode) tRHS HRD Asserted to HACK Asserted (Setup, Ready Mode) tRHH HRD Asserted to HACK Deasserted (Hold, Ready Mode) First Byte HRD Deasserted to Data Invalid (Hold) tRDH HRD Deasserted to Data Disable tRDD Timing Requirements HCMS or HCIOMS Asserted to HALE Asserted (Delay) tCSAL HALE Deasserted to Optional HCMS or HCIOMS tALCS Deasserted tRCSW HRD Deasserted to HCMS or HCIOMS Deasserted tALR HALE Deasserted to HRD Asserted tRCS HRD Deasserted (After Last Byte) to HCMS or HCIOMS Deasserted (Ready for Next Read) HALE Asserted Pulsewidth tALPW tHKRD HACK Asserted to HRD Deasserted (Hold, ACK Mode) tAALS Address Valid to HALE Deasserted (Setup) tALAH HALE Deasserted to Address Invalid (Hold)
1t NH
12tHCLK
12tHCLK 1
15tHCLK +tNH1 12 10 10 15tHCLK +tNH1
ns ns ns ns ns ns ns
10
0 1 0 5 0 4 1.5 2 4
ns ns ns ns ns ns ns ns ns
are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time. 2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
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ADSP-2191M
HCMS HIOMS
t CS A L
H ALE
tA LC S
tR C S W
tA LPW t AL R
HRD
tR C S
tR H K S
HACK ( ACK MO D E)
t HKRD
tR H K H
HA C K FOR EACH BYT E
tR H S
HAC K (R EAD Y MO DE)
tR H H
HA CK FIRST BYT E
t AL A H t A A LS
H A D15-0 H A16 AD DR ESS VAL ID ST A RT F IRST WORD D AT A VA LI D F I RST B YTE
tR D H
D ATA VAL I D L A ST B YTE
tR D D
AD DR ESS VA LID STA RT NEXT WO RD
Figure 16. Host Port ALE Mode Read Cycle Timing
REV. 0
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ADSP-2191M
Host Port ACC Mode Read Cycle Timing
Table 18 and Figure 17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 18. Host Port ACC Mode Read Cycle Timing Parameter Min Max Unit
Switching Characteristics tRHKS1 HRD Asserted to HACK Asserted (ACK Mode) First Byte HRD Asserted to HACK Asserted (Setup, ACK Mode)2 tRHKS2 tRHKH HRD Deasserted to HACK Deasserted (Hold, ACK Mode) tRHS HRD Asserted to HACK Asserted (Setup, Ready Mode) tRHH HRD Asserted to HACK Deasserted (Hold, Ready Mode) First Byte HRD Deasserted to Data Invalid (Hold) tRDH HWR Asserted to HACK Asserted (Setup) During Address tWSHKS Latch HWR Deasserted to HACK Deasserted (Hold) During tWHHKH Address Latch HRD Deasserted to Data Disable tRDD Timing Requirements HCMS or HCIOMS Asserted to HALE Asserted (Delay) tCSAL tALCS HALE Deasserted to Optional HCMS or HCIOMS Deasserted HRD Deasserted to HCMS or HCIOMS Deasserted tRCSW tALW HALE Asserted to HWR Asserted tALER HALE Deasserted to HWR Asserted tCSR HCMS or HCIOMS Asserted to HRD Asserted HRD Deasserted (After Last Byte) to HCMS or tRCS HCIOMS Deasserted (Ready for Next Read) HWR Deasserted to HALE Deasserted (Delay) tWAL tHKRD HACK Asserted to HRD Deasserted (Hold, ACK Mode) tADW Address Valid to HWR Deasserted (Setup) HWR Deasserted to Address Invalid (Hold) tWAD tHKWAL HACK Asserted to HWR Deasserted (Hold) During Address Latch2
1
12tHCLK
12tHCLK 1
15tHCLK +tNH1 10 10 10 15tHCLK +tNH1
ns ns ns ns ns ns ns ns ns
10 10 10
0 1 0 0.5 1 0 0 2.5 1.5 2 1 2
ns ns ns ns ns ns ns ns ns ns ns ns
tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time. 2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
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ADSP-2191M
HCMS HIOMS
t C SA L
HALE
tA LC S
tR C S W
t WA L tA LW
HWR
t RCS
t CS R tA LE R
HRD
t H K WA L t WSH K S
HACK (ACK MODE)
t HKRD t RHKH
HA CK EA C H BYT E
t RHKS
t WH H K H t RHS
H ACK (READY MODE)
t RHH
H A CK F IRST BYT E
tA D W
HAD 15-0 HA16 A DD RESS VALI D ST AR T FI R ST WO RD
t WA D
D ATA VAL ID F IRST B YTE
t RDH
D ATA VAL ID LA ST BYTE
t RDD
A DD RESS VA L I D S TAR T NEX T WORD
Figure 17. Host Port ACC Mode Read Cycle Timing
REV. 0
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ADSP-2191M
Serial Ports
Table 19 and Figure 18 describe SPORT transmit and receive operations, while Figure 19 and Figure 20 describe SPORT Frame Sync operations.
Table 19. Serial Ports1, 2 Parameter Min Max Unit
External Clock Timing Requirements TFS/RFS Setup Before TCLK/RCLK3 tSFSE tHFSE TFS/RFS Hold After TCLK/RCLK3 tSDRE Receive Data Setup Before RCLK3 tHDRE Receive Data Hold After RCLK3 tSCLKW TCLK/RCLK Width tSCLK TCLK/RCLK Period Internal Clock Timing Requirements TFS Setup Before TCLK4; RFS Setup Before RCLK3 tSFSI tHFSI TFS/RFS Hold After TCLK/RCLK3 tSDRI Receive Data Setup Before RCLK3 tHDRI Receive Data Hold After RCLK3 External or Internal Clock Switching Characteristics TFS/RFS Delay After TCLK/RCLK (Internally tDFSE Generated FS)4 TFS/RFS Hold After TCLK/RCLK (Internally tHOFSE Generated FS)4 External Clock Switching Characteristics Transmit Data Delay After TCLK4 tDDTE Transmit Data Hold After TCLK4 tHDTE Internal Clock Switching Characteristics Transmit Data Delay After TCLK4 tDDTI tHDTI Transmit Data Hold After TCLK4 tSCLKIW TCLK/RCLK Width Enable and Three-State5 Switching Characteristics tDTENE Data Enable from External TCLK4 tDDTTE Data Disable from External TCLK4 Data Enable from Internal TCLK4 tDTENI tDDTTI Data Disable from External TCLK4 External Late Frame Sync Switching Characteristics Data Delay from Late External TFS with MCE=1, MFD=06, 7 tDDTLFSE tDTENLFSE Data Enable from Late FS or MCE=1, MFD=06, 7
1To
4 4 1.5 4 0.5tHCLK -1 2tHCLK
ns ns ns ns ns ns
4 3 2 5
ns ns ns ns
14 3
ns ns
13.4 4
ns ns
13.4 4 0.5tHCLK -3.5 0.5tHCLK +2.5
ns ns ns
0 0
12.1 13 13 12
ns ns ns ns
10.5 3.5
ns ns
determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width. 2Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only). 3Referenced to sample edge. 4Referenced to drive edge. 5Only applies to SPORT0/1. 6MCE=1, TFS enable, and TFS valid follow t DDTENFS and tDDTLFSE. 7If external RFSD/TFS setup to RCLK/TCLK>0.5t LSCK, tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
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ADSP-2191M
DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE tSCLKIW RCLK tDFSE tHOFSE tSFSI tHFSI RFS tSDRI DR tHDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. tSDRE tHDRE RCLK tDFSE tHOFSE SAMPLE EDGE DATA RECEIVE-EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE
tSFSE
tHFSE
RFS
DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE tSCLKIW TCLK tDFSE tHOFSE tSFSI tHFSI SAMPLE EDGE
DATA TRANSMIT-EXTERNAL CLOCK DRIVE EDGE tSCLKW TCLK tDFSE tHOFSE TFS tSFSE tHFSE SAMPLE EDGE
TFS tHDTI tDDTI
tHDTE DT
tDDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE TCLK (EXT) TFS ("LATE," EXT.) tDDTEN DT DRIVE EDGE TCLK (INT) TFS ("LATE," INT.) TCLK / RCLK tDDTIN TCLK / RCLK
DRIVE EDGE
tDDTTE
DRIVE EDGE
tDDTTI DT
Figure 18. Serial Ports
REV. 0
-35-
ADSP-2191M
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE RCLK tSFSE/ I tHOSFSE/ I SAMPLE DRIVE
RFS tDTENLFSE tDDTE/ I tHDTE/ I 1ST BIT 2ND BIT
DT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE TCLK tSFSE/ I tHOSFSE/ I SAMPLE DRIVE
TFS tDTENLFSE tDDTE/ I tHDTE/ I 1ST BIT 2ND BIT
DT tDDTLFSE
Figure 19. Serial Ports--External Late Frame Sync (Frame Sync Setup > 0.5tSCLK)
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE RCLK tSFSE/ I tHOFSE/ I SAMPLE DRIVE
RFS tDTENLFSE tDDTE/ I tHDTE/ I 1ST BIT 2ND BIT
DT tDDTLFSE
LATE EXTERNAL TFS
DRIVE TCLK tSFSE/ I tHOFSE/ I SAMPLE DRIVE
TFS tDTENLFSE tDDTE/ I tHDTE/ I 1ST BIT 2ND BIT
DT tDDTLFSE
Figure 20. Serial Ports--External Late Frame Sync (Frame Sync Setup < 0.5tHCLK)
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ADSP-2191M
Serial Peripheral Interface (SPI) Port--Master Timing
Table 20 and Figure 21 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port--Master Timing Parameter Min Max Unit
Switching Characteristics tSDSCIM SPIxSEL Low to First SCLK edge (x=0 or 1) tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period Serial Clock Period tSPICLK tHDSM Last SCLK Edge to SPIxSEL High (x=0 or 1) tSPITDM Sequential Transfer Delay tDDSPID SCLK Edge to Data Output Valid (Data Out Delay) tHDSPID SCLK Edge to Data Output Invalid (Data Out Hold) Timing Requirements Data Input Valid to SCLK Edge (Data Input Setup) tSSPID tHSPID SCLK Sampling Edge to Data Input Invalid (Data In Hold)
2tHCLK -3 2tHCLK -3 2tHCLK -3 4tHCLK -1 2tHCLK -3 2tHCLK -2 0 0 8 1
6 5
ns ns ns ns ns ns ns ns ns ns
SPIxSEL ( OU T PU T) (x = 0 or 1 )
tSPICHM
tSDSCIM
SC LK (C P O L = 0 ) (O U TP U T )
tSPICLM
tSPICLK
tHDSM
t S P I TD M
tSPICLM
SC L K (C P OL = 1 ) (O U TP U T )
tSPICHM
tD D S P I D
M OS I ( OU T PU T ) MSB
tHDSPID
LS B
CPHA = 1 MIS O (IN P U T)
tS S PID
MSB V A LID
tHSPID
tSSPID
LS B V A LID
tH S PI D
tD D S P I D
MOSI ( OU TP U T) CPHA = 0 M IS O (IN PU T ) MS B
tH D S P I D
LSB
tSSPID
MSB V A L ID
tHSPID
LS B V A LID
Figure 21. Serial Peripheral Interface (SPI) Port--Master Timing
REV. 0
-37-
ADSP-2191M
Serial Peripheral Interface (SPI) Port--Slave Timing
Table 21 and Figure 22 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port--Slave Timing Parameter Min Max Unit
Switching Characteristics tDSOE SPISS Assertion to Data Out Active tDSDHI SPISS Deassertion to Data High Impedance tDDSPID SCLK Edge to Data Out Valid (Data Out Delay) SCLK Edge to Data Out Invalid (Data Out Hold) tHDSPID Timing Requirements tSPICHS Serial Clock High Period tSPICLS Serial Clock Low Period tSPICLK Serial Clock Period tHDS Last SPICLK Edge to SPISS Not Asserted Sequential Transfer Delay tSPITDS tSDSCI SPISS Assertion to First SPICLK Edge tSSPID Data Input Valid to SCLK Edge (Data Input Setup) tHSPID SCLK Sampling Edge to Data Input Invalid (Data In Hold)
0 0 0 0 2tHCLK 2tHCLK 4tHCLK 2tHCLK 2tHCLK +4 2tHCLK 1.6 2.4
8 10 10 10
ns ns ns ns ns ns ns ns ns ns ns ns
SPISS (INPUT)
tSPICHS
SCLK (CPOL = 0) (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSPICLS tSDSCI
SCLK (CPOL = 1) (INPUT)
tSPICHS
tDSOE
MISO (OUTPUT) CPHA = 1
tDDSPID
tHDSPID
MSB
tDDSPID
tDSDHI
LSB
tSSPID
MSB VALID
tHSPID
tSSPID
LSB VALID
tHSPID
MOSI (INPUT)
tDSOE
MISO (OUTPUT) CPHA = 0 MOSI (INPUT)
tDDSPID
MSB LSB
tDSDHI
tSSPID
MSB VALID LSB VALID
tHSPID
Figure 22. Serial Peripheral Interface (SPI) Port--Slave Timing
-38-
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ADSP-2191M
Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing
Figure 23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 23 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
HCLK (SAMPLE CLOCK)
RXD RECEIVE INTERNAL UART RECEIVE INTERRUPT
DATA(5-8) STOP
UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ
START TXD AS DATA WRITTEN TO BUFFER UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT DATA(5-8) STOP (1-2)
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT
Figure 23. UART Port--Receive and Transmit Timing
REV. 0
-39-
ADSP-2191M
JTAG Test And Emulation Port Timing
Table 22 and Figure 24 describe JTAG port operations.
Table 22. JTAG Port Timing Parameter Min Max Unit
Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low1 Timing Requirements TCK Period tTCK tSTAP TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High tHTAP tSSYS System Inputs Setup Before TCK Low2 tHSYS System Inputs Hold After TCK Low2 tTRSTW TRST Pulsewidth3
TFS0, TFS1, RFS0, RFS1, BMS.
0
8 22
ns ns
20 4 4 4 5 4tTCK
ns ns ns ns ns ns
1System Outputs = DATA15-0, ADDR21-0, MS3-0, RD, WR, ACK, CLKOUT, BG, PF7-0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, 2System Inputs = DATA15-0, ADDR21-0, RD, WR, ACK, BR, BG, PF7-0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, 350
CLKIN, RESET. MHz max.
tT C K
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TD O
t SS Y S
SYSTEM INPUTS
tHSYS
tD S Y S
SYSTEM O UTPUTS
Figure 24. JTAG Port Timing
-40-
REV. 0
ADSP-2191M
Output Drive Currents
Figure 25 shows typical I-V characteristics for the output drivers of the ADSP-2191M. The curves represent the current drive capability of the output drivers as a function of output voltage.
60 40
SOURCE (VDDEXT ) CURRENT - mA
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: * Number of output pins that switch during each cycle (O) * The maximum frequency at which they can switch (f) * Their load capacitance (C) * Their voltage swing (VDD) and is calculated by the formula below.
P EXT = O x C x V DD x f
2
VDDEXT = 3.65V @ - 40C VDDEXT = 3.3V @ + 25C
20 OUTPUT CURRENT 0
VOH
VDDEXT = 3.0V @ + 85C -20
V OL
-40 -60 -80
VDDEXT = 3.0V @ + 85C VDDEXT = 3.3V @ + 25C VDDEXT = 3.65V @ - 40C
INPUT CURRENT -100 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE ( VDDEXT ) VOLTAGE - V 3.5 4.0
The load capacitance includes the processor's package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. For example, estimate PEXT with the following assumptions: * A system with one bank of external data memory--asynchronous RAM (16-bit) * One 64K 16 RAM chip is used with a load of 10 pF * Maximum peripheral speed CCLK = 80 MHz, HCLK = 80 MHz * External data memory writes occur every other cycle, a rate of 1/(4tHCLK), with 50% of the pins switching * The bus cycle time is 80 MHz (tHCLK = 12.5 nsec) The PEXT equation is calculated for each class of pins that can drive as shown in Table 23.
Figure 25. Typical Drive Currents Power Dissipation
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved.
Table 23. PEXT Calculation Example Pin Type # of Pins % Switching C f VDD2 = PEXT
Address MSx WR Data CLKOUT
15 1 1 16 1
50 0 -- 50 --
10 pF 10 pF 10 pF 10 pF 10 pF
20 MHz 20 MHz 40 MHz 20 MHz 80 MHz
10.9 V 10.9 V 10.9 V 10.9 V 10.9 V
= .01635 W =0W = .00436 W = .01744 W = .00872 W PEXT =.04687 W
A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation with the following formula.
P TOTAL = P EXT + P INT
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Where: * PEXT is from Table 23 * PINT is IDDINT 2.5 V, using the calculation IDDINT listed in Power Dissipation on page 41. Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. REV. 0
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by - V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the equation below.
C L V t DECAY = --------------IL
-41-
ADSP-2191M
The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure 26. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays -V from the measured output high or output low voltage. The tDECAY is calculated with test loads CL and IL, and with -V equal to 0.5 V.
Example System Hold Time Calculation
REFERENCE SIGNAL
To determine the data output hold time in a particular system, first calculate tDECAY using the equation at Output Disable Time on page 41. Choose -V to be the difference between the ADSP-2191M's output voltage and the input threshold for the device requiring the hold time. A typical -V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tDATRWH for the write cycle).
Capacitive Loading
tMEASURED tDIS
VOH (MEASURED) VOH (MEASURED) - VOL (MEASURED) VOL (MEASURED) + V V
tENA
2.0V 1.0V
tDECAY
OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V
Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 30). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for loads other than the nominal value of 50 pF. Figure 28 and Figure 29 show how output rise time varies with capacitance. These figures also show graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on page 41.) The graphs in these figures may not be linear outside the ranges shown.
Figure 26. Output Enable/Disable
40
IOL
RISE AND FALL TIMES - ns (10%-90%)
30 RISE TIME
TO OUTPUT PIN
+1.5V 50pF
20
10
IOH
0
0
50
100
150
200
250
Figure 27. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
LOAD CAPACITANCE - pF
INPUT OR OUTPUT
Figure 29. Typical Output Rise Time (10%-90%, VDDEXT = Minimum at Maximum Ambient Operating Temperature) vs. Load Capacitance
1.5V 1.5V
Environmental Conditions
Figure 28. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time
The thermal characteristics in which the DSP is operating influence performance.
Thermal Characteristics
Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time tENA is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 26). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball Grid Array (mini-BGA) package. The ADSP-2191M is specified for an ambient temperature (TAMB) as calculated using the formula below. To ensure that the TAMB data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive.
T AMB = T CASE - PD x CA
-42-
REV. 0
ADSP-2191M
Where:
30
* TAMB = Ambient temperature (measured near top surface of package) * PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). * CA = Value from Table 24. * For the LQFP package: JC = 0.96C/W For the mini-BGA package: JC = 8.4C/W
OUTPUT DELAY OR HOLD - ns
20
10
0
Table 24. CA Values
0 50 100 150 LOAD CAPACITANCE - pF 200 250
- 10
Figure 30. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)
Airflow (Linear Ft./Min.) Airflow (Meters/Second) LQFP: CA (C/W) Mini-BGA: CA (C/W)
0 0 44.3 26
100 0.5 41.4 24
200 1 38.5 22
400 2 35.3 20.9
600 3 32.1 19.8
REV. 0
-43-
ADSP-2191M
144-Lead LQFP Pinout
Table 25 lists the LQFP pinout by signal name. Table 26 lists the LQFP pinout by pin.
Table 25. 144-Lead LQFP Pins (Alphabetically by Signal) Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No.
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 ACK BG BGH BMODE0 BMODE1 BMS BR
84 85 86 87 88 89 91 92 93 95 96 97 98 99 101 102 103 104 106 107 108 109 120 111 110 70 71 113 112
BYPASS CLKIN CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR0 DR1 DR2 DT0 DT1 DT2 EMU GND GND GND
72 132 130 123 124 125 126 128 135 136 137 138 139 140 141 142 144 1 2 60 67 49 56 64 46 81 5 16 29
GND GND GND GND GND GND GND GND GND HA16 HACK HACK_P HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HALE
33 54 55 77 80 94 105 129 134 23 26 24 3 4 6 7 8 9 10 11 12 14 15 17 18 20 21 22 30
HCMS HCIOMS HRD HWR IOMS MS0 MS1 MS2 MS3 OPMODE PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RCLK0 RCLK1 RCLK2 RD RESET RFS0 RFS1 RFS2 RXD TCK TCLK0
27 28 31 32 114 115 116 117 119 83 34 35 36 37 38 39 41 42 61 68 50 122 73 62 69 51 52 78 57
TCLK1 TCLK2 TDI TDO TFS0 TFS1 TFS2 TMR0 TMR1 TMR2 TMS TRST TXD VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT WR XTAL
65 47 75 74 59 66 48 43 44 45 76 79 53 13 25 40 63 90 100 118 131 143 19 58 82 127 121 133
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REV. 0
ADSP-2191M
Table 26. 144-Lead LQFP Pins (Numerically by Pin Number) Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
D14 D15 HAD0 HAD1 GND HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 VDDEXT HAD9 HAD10 GND HAD11 HAD12 VDDINT HAD13 HAD14 HAD15 HA16 HACK_P VDDEXT HACK HCMS HCIOMS GND
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
HALE HRD HWR GND PF0 PF1 PF2 PF3 PF4 PF5 VDDEXT PF6 PF7 TMR0 TMR1 TMR2 DT2 TCLK2 TFS2 DR2 RCLK2 RFS2 RXD TXD GND GND DT0 TCLK0 VDDINT
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
TFS0 DR0 RCLK0 RFS0 VDDEXT DT1 TCLK1 TFS1 DR1 RCLK1 RFS1 BMODE0 BMODE1 BYPASS RESET TDO TDI TMS GND TCK TRST GND EMU VDDINT OPMODE A0 A1 A2 A3
88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
A4 A5 VDDEXT A6 A7 A8 GND A9 A10 A11 A12 A13 VDDEXT A14 A15 A16 A17 GND A18 A19 A20 A21 BGH BG BR BMS IOMS MS0 MS1
117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
MS2 VDDEXT MS3 ACK WR RD D0 D1 D2 D3 VDDINT D4 GND CLKOUT VDDEXT CLKIN XTAL GND D5 D6 D7 D8 D9 D10 D11 D12 VDDEXT D13
REV. 0
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ADSP-2191M
144-Lead Mini-BGA Pinout
Table 27 lists the mini-BGA pinout by signal name. Table 28 lists the mini-BGA pinout by ball number.
Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 ACK BG BGH BMODE0 BMODE1 BMS BR
J11 H9 H10 G12 H11 G10 F12 G11 F10 F11 E12 E11 E10 E9 D11 D10 D12 C11 C12 B12 B11 A11 A8 C10 B10 L10 L9 A10 B9
BYPASS CLKIN CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR0 DR1 DR2 DT0 DT1 DT2 EMU GND GND GND
M11 A5 C6 D7 A7 C7 A6 B7 A4 C5 B5 D5 A3 C4 B4 C3 A2 B1 B2 L7 K9 L5 H6 L8 H4 J10 A1 A12 E7
GND GND GND GND GND GND GND GND GND GND HACK HACK_P HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HA16
F7 F8 F9 G4 G5 G6 H5 L6 M1 M12 H3 G1 C1 B3 C2 D1 D4 D3 D2 E1 E4 E2 F1 E3 F2 G2 F3 G3 H2
HALE HCIOMS HCMS HRD HWR IOMS MS0 MS1 MS2 MS3 OPMODE PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RCLK0 RCLK1 RCLK2 RD RESET RFS0 RFS1 RFS2 RXD TCK
J1 J3 H1 J2 K2 E8 D9 A9 C9 D8 H12 K1 L1 M2 L2 M3 L3 K3 M4 K7 J9 J5 B8 L12 K8 M10 M6 K6 K11
TCLK0 TCLK1 TCLK2 TDI TDO TFS0 TFS1 TFS2 TMR0 TMR1 TMR2 TMS TRST TXD VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT WR XTAL
J6 M9 K5 K12 L11 M8 J8 M5 K4 L4 J4 K10 J12 M7 E5 E6 F5 F6 G7 G8 H7 H8 D6 F4 G9 J7 C8 B6
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ADSP-2191M
Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5
GND D13 D9 D5 CLKIN D3 D1 ACK MS1 BMS A21 GND D14 D15 HAD1 D11 D7 XTAL D4 RD BR BGH A20 A19 HAD0 HAD2 D12 D10 D6
C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
CLKOUT D2 WR MS2 BG A17 A18 HAD3 HAD6 HAD5 HAD4 D8 VDDINT D0 MS3 MS0 A15 A14 A16 HAD7 HAD9 HAD11 HAD8 VDDEXT VDDEXT GND IOMS A13 A12
E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3
A11 A10 HAD10 HAD12 HAD14 VDDINT VDDEXT VDDEXT GND GND GND A8 A9 A6 HACK_P HAD13 HAD15 GND GND GND VDDEXT VDDEXT VDDINT A5 A7 A3 HCMS HA16 HACK
H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8
DT2 GND DT0 VDDEXT VDDEXT A1 A2 A4 OPMODE HALE HRD HCIOMS TMR2 RCLK2 TCLK0 VDDINT TFS1 RCLK1 EMU A0 TRST PF0 HWR PF6 TMR0 TCLK2 RXD RCLK0 RFS0
K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
DR1 TMS TCK TDI PF1 PF3 PF5 TMR1 DR2 GND DR0 DT1 BMODE1 BMODE0 TDO RESET GND PF2 PF4 PF7 TFS2 RFS2 TXD TFS0 TCLK1 RFS1 BYPASS GND
REV. 0
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ADSP-2191M
OUTLINE DIMENSIONS 144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)
22.00 BSC SQ 0.75 0.60 0.45 20.00 BSC SQ
144 1 109 108
0.27 0.22 TYP 0.17 SEATING PLANE 0.08 MAX LEAD COPLANARITY
0.15 0.05
1.45 1.40 1.35 1.60 MAX
36
73
37
72
DETAIL A
0.50 BSC LEAD PITCH
DETAIL A
NOTES: 1. DIMENSIONS IN MILLIMETERS. 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL.
TOP VIEW (PINS DOWN)
144-BALL MINI-BGA (CA-144A)
10.10 10.00 SQ 9.90 A1 COR NER INDEX T RIANGLE 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
8.80 BSC SQ 0.80 BSC BALL PITCH
TOP VIEW
1.70 MAX DETAIL A
BOTTOM VIEW
0.85 MIN
0.25 MIN
NOTES: 1. DIMENSIONS IN MILLIMETERS. 2. ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE TO THE PACKAGE EDGES. 3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL POSITION, RELATIVE TO THE BALL GRID. 4. CENTER DIMENSIONS ARE NOMINAL.
0.55 0.50 0.45
SEATING PLANE BALL DIAMETER 0.10 MAX BALL COPLANARITY
DETAIL A
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ADSP-2191M
ORDERING GUIDE Instruction Rate (MHz) Package Description
Part Number1, 2
Ambient Temperature Range
Operating Voltage
ADSP-2191MKST-160 ADSP-2191MBST-140 ADSP-2191MKCA-160 ADSP-2191MBCA-140
1ST 2CA
0C to 70C -40C to +85C 0C to 70C -40C to +85C
160 140 160 140
144-Lead LQFP 144-Lead LQFP 144-Ball Mini-BGA 144-Ball Mini-BGA
2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V
= Plastic Thin Quad Flatpack (LQFP). = Mini Ball Grid Array
REV. 0
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ADSP-2191M
-50-
REV. 0
ADSP-2191M
REV. 0
-51-
ADSP-2191M
-52- REV. 0
PRINTED IN U.S.A. C02936-0-4/02(0)

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